Design, Implementation and Comparison of FFT Analysis of efficient Digital PLLs for clock generation using 50nm SPICE models for CMOS

The most versatile application for digital phase locked loops is for clock generation and clock recovery in any complex computer architecture like a microprocessor or microcontroller, network processors. Digital Phase locked loops are commonly used to generate timing on chip clocks in high performance mixed signal analog and digital systems. Most of the systems employ digital PLL mainly for synchronization, skew and jitter optimization. Because of the need of high speed circuitry there is a need of PLL. Mostly communication, wireless systems, RF Processors operate in Gigahertz range, there is a necessity of PLL that too digital which operate in high order frequencies. Digital PLL is a mixed signal integrated circuit and presented work focuses on design and analysis of efficient digital phase locked loops for clock generation using 50nm SPICE models. The presented design Digital PLL performs the function of mainly generating a clock signal also consists of design of sub circuits and systems like phase detector, loop filters and voltage controlled oscillators. A detailed FFT analysis is also presented with parameters magnitude, phase and group delay calculated for each sub circuits and systems. The results of DPLL designed using proper optimization method is also compared with traditional method.